SCAN A10 Manuel d'utilisateur

9JTAG Boundary-Scan Testing in Arria 10 Devices2013.12.02A10-JTAGSubscribeSend FeedbackThis chapter describes the boundary-scan test (BST) features in

CommentsDrivesCapturesPin TypeInputUpdateRegisterOE UpdateRegisterOutputUpdateRegisterInputCaptureRegisterOE CaptureRegisterOutputCaptureRegisterPIN_I

Figure 9-3: HSSI Transmitter BSC with IEEE Std. 1149.6 BST Circuitry for Arria 10 DevicesMEM_INIT SDIN SHIFT0101D QD QCLKSDOUTMODEAC_TEST AC_MODECaptu

Document Revision HistoryChangesVersionDateInitial release.2013.12.02December 2013JTAG Boundary-Scan Testing in Arria 10 DevicesAltera CorporationSend

IDCODE (32 Bits)Product LineVariantLSB (1 Bit)ManufactureIdentity (11 Bits)Part Number (16 Bits)Version (4 Bits)1000 0110 11100010 1110 0100 01100000G

DescriptionInstruction CodeJTAG Instruction• Places the 1-bit bypass registerbetween the TDI and TDO pins.During normal device operation,the 1-bit byp

DescriptionInstruction CodeJTAG Instruction• Places the 1-bit bypass registerbetween the TDI and TDO pins.During normal operation, the 1-bitbypass reg

JTAG Secure ModeIn the JTAG secure mode, the JTAG pins support only the BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE,and USERCODE JTAG instructions.JTAG Pri

To issue other JTAG instructions, follow these guidelines:•To perform testing before configuration, hold the nCONFIG pin low.•To perform BST during co

Connection for DisablingJTAG Pins(2)VCCPGMTDILeave openTDOGNDTRSTGuidelines for IEEE Std. 1149.1 Boundary-Scan TestingConsider the following guideline

Figure 9-1: Boundary-Scan RegisterThis figure shows how test data is serially shifted around the periphery of the IEEE Std. 1149.1 device.TCKTMSTDI TD

Figure 9-2: User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Arria 10 Devices01010101010101D QInputD QInputD QOED QOED QOutputD QOutputGlobalSigna